The invention is more particularly applicable for producing MIS or CMOS integrated circuits exhibiting high operating speeds.
The known silicon technology on a nonconductor known under the abbreviation SOI, compared with standard techniques for forming circuits on a massive silicon monocrystalline substrate, is able to reduce parasitic capacities between the active zones and the substrate and thus increase the speed of functioning, increase the integration density and has better resistance to high voltages and low sensitivity to radiations.
There are various techniques for forming a thin film of silicon on a nonconductor. One of these techniques involves the laser recrystallization of an amorphous or polycrystalline silicon film laid on a nonconducting support. This support may be sapphire (technology known under the abbreviation SOS) or a film of silicon oxide obtained via thermal oxidation of a monocrystaline silicon substrate.
A second technique known under the abbreviation BESOI (Bonded and Etched SOI) consists of bonding two substrates with silicon with at least one of them having on the bonding surface a film of SiO2 obtained by thermal oxidation and of then thinning one of the two substrates until the desired thickness is obtained.
A third known technique is based on the ion implantation of a high dose of oxygen or nitrogen in the massive monocrystalline silicon which, once the substrate has been annealed at a high temperature, results in the formation of a nonconducting buried film of silicon oxide or nitride supporting the thin film of monocrystalline silicon. The technology using the implantation of oxygen ions is known under the SIMOX terminology.
The invention is in particular applicable to these various SOI techniques.
The future of SOI lines of products passes through the reduction of the thickness of the silicon film down to about 30 nm in the channel of the transistor, whereas traditionally it is initially 200 nm on the substrates. The problem of using specially thinned substrates so as to finally obtain the desired thickness means that the entire film is thinned, which is suitable for the active portion of the transistor (channel) but results in significant problems for the current gaining access in the drain and source zones of the transistor, in particular due to the fact that the access resistance becomes too considerable in such a thin film.
This problem of parasitic access resistance is described in detail in the document (1) by Y. Omura and al., IEDM 91, CH 3075, p. 675-678, "0.1 .mu.m gate, ultrathin-film CMOS devices using SIMOX substrate with 80 nm thick buried oxide layer" or again in the document (2) by D. Hisamoto and al., IEEE 1992 (4) 7 803-0817, p. 829-832, "Ultra-thin SOI CMOS with selective CVD tungsten for low resistance source and drain".
One of the solutions put forward is to compensate for the reduction of the thickness of the silicon on the source and drain zones by means of a local epitaxial growth of silicon outside the active zone of the transistor and consequently in the source and drain regions. Unfortunately, this stage is extremely difficult to implement and has not been industrialized.
Another solution consists of using an extremely thin film of silicon (&lt;100 nm) to be silicided on a small thickness in the source and drain zones, as described in the document (3) IEEE transactions on Electron Devices, vol. 39, No 5, May 1992 by Y. Yamagushi and al., "Self-aligned silicide technology for ultra-thin SIMOX MOSFET's", p. 1179-1183. Unfortunately, this siliciding on an extremely small thickness poses significant technological problems.